In Chapter 3 we looked at fault simulation. Its purpose is to evaluate test programs in order to measure their effectiveness at distinguishing between faulty and fault-free circuits. The question of the origin of test stimuli was ignored for the moment; we simply noted that test programs could be derived from test stimuli originally intended for design verification, or stimuli could be written specifically for the purpose of exercising the circuit to reveal the presence of physical defects, or stimuli could be produced by an automatic test pattern generator (ATPG). We now turn our attention to the ATPG. However, we. | CHAPTER 4 Automatic Test Pattern Generation INTRODUCTION In Chapter 3 we looked at fault simulation. Its purpose is to evaluate test programs in order to measure their effectiveness at distinguishing between faulty and fault-free circuits. The question of the origin of test stimuli was ignored for the moment we simply noted that test programs could be derived from test stimuli originally intended for design verification or stimuli could be written specifically for the purpose of exercising the circuit to reveal the presence of physical defects or stimuli could be produced by an automatic test pattern generator ATPG . We now turn our attention to the ATPG. However we also examine two alternatives to fault simulation in this chapter testdetect and critical path tracing. These two methods share much common terminology as well as methodology with corresponding ATPGs so it is convenient to group them with their corresponding ATPGs. A number of techniques have emerged over the past three decades to generate test programs for digital circuits. For combinational circuits several of these including D-algorithm PODEM FAN and Boolean differences have been shown to be true algorithms in the sense that given enough time they will eventually come to a halt that is there is a stopping rule. If one or more tests exist for a given fault they will identify the test s . For sequential circuits as we will see in the next chapter no such statement can be made. Push-button solutions capable of automatically generating comprehensive test programs for sequential circuits require assistance in the form of design-for-test DFT which will be a subject for a later chapter. In this chapter we will examine the algorithms and procedures for combinational logic and attempt to understand their strengths and weaknesses. THE SENSITIZED PATH In Section while discussing the stuck-at fault model it was pointed out that whenever fault modeling alternatives were considered combinatorial .
