The first five chapters provided a survey of algorithms for logic simulation, fault simulation, and automatic test pattern generation. That was followed by a brief survey of tester architectures and strategies to maximize tester effectiveness while minimizing overall test cost. We now turn our attention to methods for combining the various algorithms and testers in ways that make it possible to achieve quality levels consistent with product requirements and design methodologies. | CHAPTER 7 Developing a Test Strategy INTRODUCTION The first five chapters provided a survey of algorithms for logic simulation fault simulation and automatic test pattern generation. That was followed by a brief survey of tester architectures and strategies to maximize tester effectiveness while minimizing overall test cost. We now turn our attention to methods for combining the various algorithms and testers in ways that make it possible to achieve quality levels consistent with product requirements and design methodologies. It has been recognized for some time now that true automatic test pattern generation is a long way from realization meaning that software capable of automatically generating high-quality tests for most general sequential logic circuits does not currently exist nor is it likely to exist in the forseeable future. Hence it is necessary to incorporate testability structures in digital designs to make them testable. We begin this chapter with a look at the design and test environment. That will provide a framework for discussion of the various topics related to test and will help us to see how the individual pieces fit together. Most importantly by starting with a comprehensive overview of the total design and test process we can identify opportunities to port test stimuli created during design verification into the manufacturing test development process. After examining the design and test environment we will take an in-depth look at fault modeling because in the final analysis the fault model that is chosen will have a significant effect on the quality of the test. Other topics that fit into a comprehensive design and test framework including design-for-test DFT and built-in-self-test BIST will be discussed in subsequent chapters. THE TEST TRIAD Several strategies exist for developing test programs for digital ICs these include Functional vectors Fault-directed vectors IDDQ Digital Logic Testing and Simulation Second Edition by Alexander
