ARM Architecture Reference Manual- P3: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | Programmer s Model Also in many implementations the IMB sequence includes operations that are only usable from privileged processor modes such as the cache cleaning and invalidation operations supplied by the standard System Control coprocessor see Chapter B5 Caches and Write Buffers . To allow User mode programs to use the IMB sequence it is recommended that it is supplied as an operating system call invoked by a SWI instruction. In systems that use the 24-bit immediate in a SWI instruction to specify the required operating system service it is recommended that the IMB sequence is requested by the instruction SWI 0XF00000 This call takes no parameters and does not return a result and should use the same calling conventions as a call to a C function with prototype void IMB void apart from the fact that a SWI instruction is used for the call rather than a BL instruction. Some implementations can use knowledge of the range of addresses to which new instructions have been stored to reduce the execution time cost of an IMB. It is therefore also recommended that a second operating system call is supplied which does an IMB with respect to a specified address range only. On systems that use the 24-bit immediate in a SWI instruction to specify the required operating system service this should be requested by the instruction SWI 0XF00001 and should use similar calling conventions to those used by a call to a C function with prototype void IMB_Range unsigned long start_addr unsigned long end_addr where the address range runs from start_addr inclusive to end_addr exclusive . ------Note ----------------- When the standard ARM Procedure Calling Standard is used this means that start_addr is passed in R0 and end_addr in R1. On some ARM implementations the execution time cost of an IMB can be very large many thousands of clock cycles even when a small address range is specified. For small scale uses of self-modifying code this is likely to lead to a major loss of performance. It
