ARM Architecture Reference Manual- P9: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | ARM Addressing Modes Load and Store Word or Unsigned Byte - Register pre-indexed 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0 cond 0 1 1 1 U B 1 L Rn Rd 00000000 Rm This addressing mode calculates an address by adding or subtracting the value of an index register Rm to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-5. Syntax Rn - Rm where Rn Specifies the register containing the base address. Rm Specifies the register containing the offset to add to or subtract from Rn. Sets the W bit causing base register update. Architecture version All Operation if U 1 then address Rn Rm else U 0 address Rn - Rm if ConditionPassed cond then Rn address Notes Encoding This addressing mode is encoded as an LSL scaled register offset scaled by zero. The B bit This bit distinguishes between an unsigned byte B 1 and a word B 0 access. The L bit This bit distinguishes between a Load L 1 and a Store L 0 instruction. Use of R15 Specifying R15 as register Rm or Rn has UNPREDICTABLE results. Operand restriction If the same register is specified for Rn and Rm the result is UNPREDICTABLE. ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. A5-25 ARM Addressing Modes Load and Store Word or Unsigned Byte - Scaled register pre-indexed 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 76543 0 cond 0 1 1 1 U B 1 L Rn Rd shift_imm shift 0 Rm These five addressing modes calculate an address by adding or subtracting the shifted or rotated value of the index register Rm to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-5. Syntax One of Rn - Rm LSL shift_imm Rn - Rm
