ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE- P2: Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. | Representation of Systems endmodule A module instantiation in the Verilog-A language is similar to a variable declaration in programming languages. The module type name declares the module instance type followed by optional parameter settings within the . construct the instance name and the connection list. From Listing the following is used to illustrate the module instantiation syntax type of the module instance name of the instance created qam_mod .carrier_freq fc mod cin din elk parameter name in child qam_mod module assigned as carrierjreq fc The module type name qam_mod creates the instance named mod. The mod instance is passed the value fc as the value for the parameter carrier_freq to the instance. The instance is connected to signals cin din and clk within the definition of the module modem. The instantiation for the qam_mod instance mod and the other two component instantiations within the modem module definition in Listing declares the design hierarchy of Figure . module qam instance mod instance c1 instance demod module qam_mod module channel module qam_demod figure Hierarchical view of the modem system. Structural definitions in the Verilog-A language facilitate the use of top-down design methodologies. As architectural design progresses structural and behavioral definitions with finer details of description can be substituted for determining the system Analog System Description and Simulation 15 Please purchase PDF Split-Merge on to remove this watermark Analog System Description and Simulation performance to specifications. Utilizing this capability requires no more than an understanding of the parameter and port definitions of a module. Behavioral Descriptions The Verilog-A language provides for describing the behavior of analog and mixedsignal systems. The analog behavioral descriptions are encapsulated within analog statements or blocks within a module definition. The behavioral descriptions are mathematical .
