ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE- P5: Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. | Module Instantiations ports listed for the module instance must be in the same order as the ports listed in the module definition. For example in the a2d module defined previously ----------------------------port 1 ----------------------------port 2 ----------------------------port 3 ---------------------------- port 4 ---------------------------- port 5 j--------------------------- port 6 module a2d d0 dl d2 d3 in elk input in elk output dO dl d2 d3 electrical in elk electrical dO dl d2 d3 parameter real tdel lOn parameter real trise lOn parameter real tfall lOn The following instantiates a components msb_a2d of the a2d module defined above a2d .vrange msb_a2d bit4 bit5 corresponding X X port in module a2d dO d1 The second way to connect module ports consists of explicitly linking the two names for each side of the connection - the name used in the module definition followed by the name used in the instantiating module. This compound name is then placed in the list of module connections. The name of the port must be the name specified in the module definition same as for parameters . Using connection by name the previous example can be rewritten Declarations and Structural Descriptions 105 Please purchase PDF Split-Merge on to remove this watermark Declarations and Structural Descriptions a2d .vrange msb_a2d .d0 bit4 .d1 bit5 .d2 bit6 .d3 bit7 .in in .clk clock lsb_a2d .d0 bit0 .dl bitl .d2 bit2 .d3 bit3 .in gain_out .clk clock The two types of module port connections can not be mixed connections to the ports of a particular module instance must be all by order or all by name. The are rules governing the way module ports are declared and the way they are interconnected. The most important of which is that all ports connected to a node must be compatible with each other as well as to the discipline of the node1. 1. The node of any discipline type is compatible in a connection to the ground or reference node. 106 Verilog-A HDL Please purchase
