ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE- P8: Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. | Verilog-A Explorer IDE signal icon within the hierarchy view of the Project Navigator. For example doubleclicking on signal icon out results in shown in Figure . FIGURE Plotting signals within the IDE. To plot a signal raise the plot window and double-click on the signal icon of interest in the hierarchy navigator. To delete a trace click on a signal name in the plot legend to select. Delete with the DEL key. Signals can be deleted from the plot view by clicking on the signal within the plot legend. This will select the signal by placing a box around the name. If a signal is selected it can be deleted simply by pressing the DEL key. Zooming in on a specific area of the plot view is accomplished by left-mouse button drag operations. To zoom back out press the right-mouse button in the plot window and choose either Zoom To Fit or Zoom Out. 196 Verilog-A HDL Please purchase PDF Split-Merge on to remove this watermark Using the Explorer IDE After a plot has been selected you can change its properties via the Plot Properties dialog accessible from the right-mouse button within the plot window. The Plot Properties dialog allows you to set generic axis and signal attributes. Generic plot attributes include the plot type as well as display of titles and or subtitles. Axis properties of the plot allow you to set the axis styles for both the X- and Y-axis including labels and tic-mark styles. Verilog-A Explorer IDE 197 Please purchase PDF Split-Merge on to remove this watermark Verilog-A Explorer IDE Signal properties allow you to edit the description of the signals displayed in the legend box as well as the data format and drawing attributes. Creating a New Designs Starting a new design follows essentially the same procedure as previously outlined but with the addition to creating a new circuit and or Verilog-A file s . From the main Explorer menu select File- New which raises the following dialog box If you select a circuit .
