Segment Design Tradeoffs I. OVERVIEW The six steps in the systems-level design process associated with the software radio are illustrated in Figure 6-1. The tradeoffs proceed from front end to back end. The choice of antennas (step 1 in the figure) determines the number and bandwidth of RF channels (step 2). This, in turn, constrains the numbers and bandwidths of ADCs (step 3). Some waveforms may require dedicated ASICs (., W-CDMA despreaders) in front of the ADCs. Additional parallel IF processing and ADC paths may be necessary to support multiple-service bands simultaneously | Software Radio Architecture Object-Oriented Approaches to Wireless Systems Engineering Joseph Mitola III Copyright @2000 John Wiley Sons Inc. ISBNs 0-471-38492-5 Hardback 0-471-21664-X Electronic 6 Segment Design Tradeoffs I. OVERVIEW The six steps in the systems-level design process associated with the software radio are illustrated in Figure 6-1. The tradeoffs proceed from front end to back end. The choice of antennas step 1 in the figure determines the number and bandwidth of RF channels step 2 . This in turn constrains the numbers and bandwidths of ADCs step 3 . Some waveforms may require dedicated ASICs . W-CDMA despreaders in front of the ADCs. Additional parallel IF processing and ADC paths may be necessary to support multiple-service bands simultaneously. The ADCs provide high-speed streams for heterogeneous multiprocessing step 4 . Digital interconnect fans these streams out to digital-filter ASICs. The resulting narrowband streams then interleave among DSPs medium-speed interconnect and general-purpose processors yielding a multithreaded multitasking multiprocessing operating environment. Software objects must be organized into real-time objects step 5 . The effective hosting of these objects onto this complex operating environment requires a refined set of techniques unique to this text called SDR performance management step 6 . These six tradeoff steps are introduced in this section and discussed in depth in the subsequent chapters. Personality Mmpy 100 fs Mmpy 40 Wc IPS 100 Rb I V 1 1 A 1 IF Processing Baseband Bitstream Audio 1 RF T D 1 Object Object Object 1 ADAC Conversion c - ZZZZZ3ZZZZZZZZZ- _ 5 ASIC k J i Control k User Object fs Ĩ N log SFDR 2 I 2 MFLOPS 100 fs Wc Rb 4 106 . ft MEOPS MFÇOPS 2 Efficiency_ I. _ ÍC Wa Power I Ifs n RF 1 j ASIC 1 k. 4 ụ J fs N I 10 mW DSP - RAM ASIC MOPS Provided 50 MIPS 20 MFLOPS 50MEmoryOPS 100 BusOPS. 250mW Host s Rb1 User 4mW Rb 4 Figure 6-1 Six-step segment design-tradeoff process. 236 .
