Digital Processing Tradeoffs This chapter addresses digital hardware architectures for SDRs. A digital hardware design is a configuration of digital building blocks. These include ASICs, FPGAs, ADCs, DACs, digital interconnect, digital filters, DSPs, memory, bulk storage, I/O channels, and/or general-purpose processors. A digital hardware architecture may be characterized via a reference platform, the minimum set of characteristics necessary to define a consistent family of designs of SDR hardware | Software Radio Architecture Object-Oriented Approaches to Wireless Systems Engineering Joseph Mitola III Copyright 2000 John Wiley Sons Inc. ISBNs 0-471-38492-5 Hardback 0-471-21664-X Electronic 10 Digital Processing Tradeoffs This chapter addresses digital hardware architectures for SDRs. A digital hardware design is a configuration of digital building blocks. These include ASICs FPGAs ADCs DACs digital interconnect digital filters DSPs memory bulk storage I O channels and or general-purpose processors. A digital hardware architecture may be characterized via a reference platform the minimum set of characteristics necessary to define a consistent family of designs of SDR hardware. This chapter develops the core technical aspects of digital hardware architecture by considering the digital building blocks. These insights permit one to characterize the architecture tradeoffs. From those tradeoffs one may derive a digital reference platform capable of embracing the necessary range of digital hardware designs. The chapter begins with an overview of digital processing metrics and then describes each of the digital building blocks from the perspective of its SDR architecture implications. I. METRICS Processors deliver processing capacity to the radio software. The measurement of processing capacity is problematic. Candidate metrics for processing capacity are shown in Table 10-1. Each metric has strengths and limitations. One goal of architecture analysis is to define the relationship between these metrics and achievable performance of the SDR. The point of view employed is that one must predict the performance of an unimplemented software suite on an unimplemented hardware platform. One must then manage the computational demands of the software against the benchmarked capacities of the hardware as the product is implemented. Finally one must determine whether an existing software personality is compatible with an existing hardware suite. TABLE 10-1 Processing Metrics .
