ATM Switching with Non-Blocking Multiple-Queueing Networks We have seen in the previous chapter how a non-blocking switch based on a single queueing strategy (input, output, or shared queueing) can be implemented and what traffic performance can be expected. Here we would like to investigate how two of the three different queueing strategies can be combined in the design of a non-blocking ATM switch. The general structure of a non-blocking switch with size N × M is represented in Figure . Each input port controller (IPC) and output port controller (OPC) are provided with a FIFO buffer of size B i and. | Switching Theory Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright 1998 John Wiley Sons Ltd ISBNs 0-471-96338-0 Hardback 0-470-84191-5 Electronic Chapter 8 ATM Switching with Non-Blocking Multiple-Queueing Networks We have seen in the previous chapter how a non-blocking switch based on a single queueing strategy input output or shared queueing can be implemented and what traffic performance can be expected. Here we would like to investigate how two of the three different queueing strategies can be combined in the design of a non-blocking ATM switch. The general structure of a non-blocking switch with size N X M is represented in Figure . Each input port controller IPC and output port controller OPC are provided with a FIFO buffer of size B. and Bg cells respectively. A FIFO shared buffer with capacity NBs cells is also associated with the non-blocking interconnection network IN . Therefore B. Bg and Bs represent the input output and shared capacity per input-output port in a squared switch. Apparently having Bx 0 for x i o s corresponds to absence of input output and shared queueing respectively. Usually unless required by other considerations IPC and OPC with the same index are implemented as a single port controller PC interfacing an input and an output channel so that the switch becomes squared. Unless stated otherwise a N X N squared switch is considered in the following and its size N is a power of 2. Output queueing is adopted when the interconnection network is able to transfer more than one cell to each OPC since only one cell per slot can leave the OPC. Then the switch is said to have an output speed-up K meaning that up to K packets per slot can be received by each OPC. Note that the condition K min Bg N always applies. While the second bound is determined by obvious physical considerations the former bound is readily explained considering that it would make no sense to feed the output queue in a slot with a number of .
