ATM Switching with Arbitrary-Depth Blocking Networks We have seen in Chapter 6 how an ATM switch can be built using an interconnection network with “minimum” depth, in which all packets cross the minimum number of self-routing stages that guarantees the network full accessibility, so as to reach the addresses switch outlet. It has been shown that queueing, suitable placed inside or outside the interconnection network, allows the traffic performance typical of an ATM switch. | Switching Theory Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright 1998 John Wiley Sons Ltd ISBNs 0-471-96338-0 Hardback 0-470-84191-5 Electronic Chapter 9 ATM Switching with Arbitrary-Depth Blocking Networks We have seen in Chapter 6 how an ATM switch can be built using an interconnection network with minimum depth in which all packets cross the minimum number of self-routing stages that guarantees the network full accessibility so as to reach the addresses switch outlet. It has been shown that queueing suitable placed inside or outside the interconnection network allows the traffic performance typical of an ATM switch. The class of ATM switching fabric described in this Chapter is based on the use of very simple unbuffered switching elements SEs in a network configuration conceptually different from the previous one related to the use of banyan networks. The basic idea behind this new class of switching fabrics is that packet loss events that would occur owing to multiple packets requiring the same interstage links are avoided by deflecting packets onto unrequested output links of the switching element. Therefore the packet loss performance is controlled by providing several paths between any inlet and outlet of the switch which is generally accomplished by arranging a given number of self-routing stages cascaded one to other. Therefore here the interconnection network is said to have an arbitrary depth since the number of stages crossed by packets is variable and depends on the deflections occurred to the packets. Now the interconnection network is able to switch more than one packet per slot to a given switch output interface so that queueing is mandatory on the switch outputs since at most one packet per slot can be transmitted to each switch outlet. As in the previous chapters a switch architecture of size N X N will be considered with the notation n log2N. Nevertheless unlike architectures based on banyan networks now n no .
