In recent years, the technological trend toward high-performance mobile communications devices has caused a burgeoning interest in the field of low-power design. Indeed, with the proliferation of portable devices such as digital cellular phones, pagers and personal digital assistants, designing for low-power with high throughput is becoming increasingly necessary. It is often claimed that a full-custom ASIC will be ‘‘lower power’’ than a programmable approach. This is certainly the case when compared to a general purpose processor, but less apparent when compared to a programmable Digital Signal Processor (DSP) processor [13] | The Application of Programmable DSPs in Mobile Communications Edited by Alan Gatherer and Edgar Ausländer Copyright 2002 John Wiley Sons Ltd ISBNs 0-471-48643-4 Hardback 0-470-84590-2 Electronic 15 Benchmarking DSP Architectures for Low Power Applications David Hwang Cimarron Mittelsteadt and Ingrid Verbauwhede Introduction In recent years the technological trend toward high-performance mobile communications devices has caused a burgeoning interest in the field of low-power design. Indeed with the proliferation of portable devices such as digital cellular phones pagers and personal digital assistants designing for low-power with high throughput is becoming increasingly necessary. It is often claimed that a full-custom ASIC will be lower power than a programmable approach. This is certainly the case when compared to a general purpose processor but less apparent when compared to a programmable Digital Signal Processor DSP processor 13 . An experiment has been designed to verify this claim for a realistic signal processing application in a low-power environment 2 . The goal is to quantify this claim. A meaningful example one quite larger than a simple FIR filter or autocorrelation will for the most part execute signal processing functions but will also include some control code and book-keeping operations encountered in many signal processing applications. A Linear Prediction Coefficient LPC speech coder was chosen for this task. It is described in subsequent paragraphs. Secondly the design methodologies for each design approach ASIC or programmable DSP will be explained and compared in design effort. This chapter will investigate five signal processing specific platforms three programmable DSP processors - the TI C55x the TI C54x and the TI C6x and two signal processing design environments - Ocapi and AIRT Designer. Each design is optimized to reduce cycle count and power consumption. All five designs will be compared based on energy area clock frequency MIPS .
