Ports provide the interface by which a module can communicate with its environment. For example, the input/output pins of an IC chip are its ports. | .2 Ports Ports provide the interface by which a module can communicate with its environment. For example the input output pins of an IC chip are its ports. The environment can interact with the module only through its ports. The internals of the module are not visible to the environment. This provides a very powerful flexibility to the designer. The internals of the module can be changed without affecting the environment as long as the interface is not modified. Ports are also referred to as terminals. List of Ports A module definition contains an optional list of ports. If the module does not exchange any signals with the environment there are no ports in the list. Consider a 4-bit full adder that is instantiated inside a top-level module Top. The diagram for the input output ports is shown in Figure 4-3. Figure 4-3. I O Ports for Top and Full Adder Notice that in the above figure the module Top is a top-level module. The module fulladd4 is instantiated below Top. The module fulladd4 takes input on ports a b and c_in and produces an output on ports sum and c_out. Thus module fulladd4 performs an addition for its environment. The module Top is a top-level module in the simulation and does not need to pass signals to or receive signals from the environment. Thus it does not have a list of ports. The module names and port lists for both module declarations in Verilog are as shown in Example 4-2. Example 4-2 List of Ports module fulladd4 sum c_out a b c_in Module with a list of ports module Top No list of ports top-level module in simulation Port Declaration All ports in the list of ports must be declared in the module. Ports can be declared as follows Verilog Keyword Type of Port input Input port Verilog Keyword Type of Port output inout Output port Bidirectional port Each port in the port list is defined as input output or inout based on the direction of the port signal. Thus for the example of the fulladd4 in Example 4-2 the port declarations will be as
