Hierarchical Names We described earlier how Verilog supports a hierarchical design methodology. Every module instance, signal, or variable is defined with an identifier. | Hierarchical Names We described earlier how Verilog supports a hierarchical design methodology. Every module instance signal or variable is defined with an identifier. A particular identifier has a unique place in the design hierarchy. Hierarchical name referencing allows us to denote every identifier in the design hierarchy with a unique name. A hierarchical name is a list of identifiers separated by dots . for each level of hierarchy. Thus any identifier can be addressed from any place in the design by simply specifying the complete hierarchical name of that identifier. The top-level module is called the root module because it is not instantiated anywhere. It is the starting point. To assign a unique name to an identifier start from the top-level module and trace the path along the design hierarchy to the desired identifier. To clarify this process let us consider the simulation of SR latch in Example 4-1. The design hierarchy is shown in Figure 4-5. Figure 4-5. Design Hierarchy for SR Latch Simulation For this simulation stimulus is the top-level module. Since the top-level module is not instantiated anywhere it is called the root module. The identifiers defined in this module are q qbar set and reset. The root module instantiates m1 which is a module of type SR_latch. The module ml instantiates nand gates n1 and n2. Q Qbar S and R are port signals in instance ml. Hierarchical name referencing assigns a unique name to each identifier. To assign hierarchical names use the module name for root module and instance names for all module instances below the root module. Example 4-8 shows hierarchical names for all identifiers in the above simulation. Notice that there is a dot . for each level of hierarchy from the root module to the desired identifier. Example 4-8 Hierarchical Names stimulus Each identifier in the .
