Examples A design can be represented in terms of gates, data flow, or a behavioral description. In this section, we consider the 4-to-1 multiplexer | Examples A design can be represented in terms of gates data flow or a behavioral description. In this section we consider the 4-to-1 multiplexer and 4-bit full adder described in Section Examples. Previously these designs were directly translated from the logic diagram into a gate-level Verilog description. Here we describe the same designs in terms of data flow. We also discuss two additional examples a 4-bit full adder using carry lookahead and a 4-bit counter using negative edge-triggered D-flipflops. 4-to-1 Multiplexer Gate-level modeling of a 4-to-1 multiplexer is discussed in Section Examples. The logic diagram for the multiplexer is given in Figure 5-5 and the gate-level Verilog description is shown in Example 5-5. We describe the multiplexer using dataflow statements. Compare it with the gate-level description. We show two methods to model the multiplexer by using dataflow statements. Method 1 logic equation We can use assignment statements instead of gates to model the logic equations of the multiplexer see Example 6-2 . Notice that everything is same as the gate-level Verilog description except that computation of out is done by specifying one logic equation by using operators instead of individual gate instantiations. I O ports remain the same. This is important so that the interface with the environment does not change. Only the internals of the module change. Notice how concise the description is compared to the gate-level description. Example 6-2 4-to-1 Multiplexer Using Logic Equations Module 4-to-1 multiplexer using data flow. logic equation Compare to gate-level model module mux4_to_1 out i0 i1 i2 i3 s1 s0 Port declarations from the I O diagram output out input i0 i1 i2 i3 input s1 s0 Logic equation for out assign out s1 s0 i0 s1 s0 i1 s1 s0 i2 s1 s0 i3 endmodule Method 2 conditional operator There is a more concise way to specify the 4-to-1 multiplexers. In Section Conditional Operator we described how a conditional .
