Verilog Programming part 20

Loops There are four types of looping statements in Verilog: while, for, repeat, and forever. The syntax of these loops is very similar to the syntax of loops in the C programming language. | Loops There are four types of looping statements in Verilog while for repeat and forever. The syntax of these loops is very similar to the syntax of loops in the C programming language. All looping statements can appear only inside an initial or always block. Loops may contain delay expressions. While Loop The keyword while is used to specify this loop. The while loop executes until the while-expression is not true. If the loop is entered when the while-expression is not true the loop is not executed at all. Each expression can contain the operators in Table 6-1 on page 96. Any logical expression can be specified with these operators. If multiple statements are to be executed in the loop they must be grouped typically using keywords begin and end. Example 7-22 illustrates the use of the while loop. Example 7-22 While Loop Illustration 1 Increment count from 0 to 127. Exit at count 128. Display the count variable. integer count initial begin count 0 while count 128 Execute loop till count is 127. exit at count 128 begin display Count d count count count 1 end end Illustration 2 Find the first bit with a value 1 in flag vector variable define TRUE 1 b1 define FALSE 1 b0 reg 15 0 flag integer i integer to keep count reg continue initial begin flag 16 b 0010_0000_0000_0000 i 0 continue TRUE while i 16 continue Multiple conditions using operators. begin if flag i begin display Encountered a TRUE bit at element number d i continue FALSE end i i 1 end end For Loop The keyword for is used to specify this loop. The for loop contains three parts An initial condition A check to see if the terminating condition is true A procedural assignment to change value of the control variable The counter described in Example 7-22 can be coded as a for loop Example 7-23 . The initialization condition and the incrementing procedural assignment are included in the for loop and do not need to be specified separately. Thus the for loop provides a more compact loop structure .

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