Generate Blocks Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins. This facilitates the creation of parametrized models. | Generate Blocks Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins. This facilitates the creation of parametrized models. Generate statements are particularly convenient when the same operation or module instance is repeated for multiple bits of a vector or when certain Verilog code is conditionally included based on parameter definitions. Generate statements allow control over the declaration of variables functions and tasks as well as control over instantiations. All generate instantiations are coded with a module scope and require the keywords generate - endgenerate. Generated instantiations can be one or more of the following types Modules User defined primitives Verilog gate primitives Continuous assignments initial and always blocks Generated declarations and instantiations can be conditionally instantiated into a design. Generated variable declarations and instantiations can be multiply instantiated into a design. Generated instances have unique identifier names and can be referenced hierarchically. To support interconnection between structural elements and or procedural blocks generate statements permit the following Verilog data types to be declared within the generate scope net reg integer real time realtime event Generated data types have unique identifier names and can be referenced hierarchically. Parameter redefinition using ordered or named assignment or a defparam statement can be declared with the generate scope. However a defparam statement within a generate scope is allowed to modify the value of a parameter only in the same generate scope or within the hierarchy instantiated within the generate scope. Task and function declarations are permitted within the generate scope but not within a generate loop. Generated tasks and functions have unique identifier names and can be referenced hierarchically. Some module declarations and module items are not permitted in a generate .
