Exercises 1: A 4-bit full adder with carry lookahead was defined in Example 6-5 on page 109, using an RTL description. Synthesize the full adder, using a technology library available to you. | Exercises 1 A 4-bit full adder with carry lookahead was defined in Example 6-5 on page 109 using an RTL description. Synthesize the full adder using a technology library available to you. Optimize for fastest timing. Apply identical stimulus to the RTL and the gate-level netlist and compare the output. 2 A 1-bit full subtractor has three inputs x y and z previous borrow and two outputs D difference and B borrow . The logic equations for D and B are as follows D x y z x yz xy z xyz B x y x z yz Write the Verilog RTL description for the full subtractor. Synthesize the full subtractor using any technology library available to you. Optimize for fastest timing. Apply identical stimulus to the RTL and the gate-level netlist and compare the output. 3 Design a 3-to-8 decoder using a Verilog RTL description. A 3-bit input a 2 0 is provided to the decoder. The output of the decoder is out 7 0 . The output bit indexed by a 2 0 gets the value 1 the other bits are 0. Synthesize the decoder using any technology library available to you. Optimize for smallest area. Apply identical stimulus to the RTL and the gate-level netlist and compare the outputs. 4 Write the Verilog RTL description for a 4-bit binary counter with synchronous reset that is active high. Hint Use always loop with the @ posedge clock statement. Synthesize the counter using any technology library available to you. Optimize for smallest area. Apply identical stimulus to the RTL and the gate-level netlist and compare the outputs. 5 Using a synchronous finite state machine approach design a circuit that takes a single bit stream as an input at the pin in. An output pin match is asserted high each time a pattern 10101 is detected. A reset pin initializes the circuit synchronously. Input pin clk is used to clock the circuit. Synthesize the circuit using any technology library available to you. Optimize for fastest timing. Apply identical stimulus to the RTL and the gate-level netlist and compare the outputs. Team
