Hardware and Computer Organization- P4:Today, we often take for granted the impressive array of computing machinery that surrounds us and helps us manage our daily lives. Because you are studying computer architecture and digital hardware, you no doubt have a good understanding of these machines, and you’ve probably written countless programs on your PCs and workstations. | Chapter 4 at logic 0 . This means that the upper NAND gate s two inputs are 1 and 0 the lower NAND gate s inputs are both 1. From the truth table for a NAND gate we see that this circuit is stable because the inputs and outputs are all in their correct logic state. Now let s perturb this stable system by applying a negative pulse to input A. Now things will change very rapidly. The output of the lower NAND gate goes to 1 because the inputs are now 1 and 0. The 1 is now applied to the input of the upper NAND gate so the output goes to 0 since both inputs are 1. The output of the upper NAND gate is simultaneously applied to the input of the lower NAND gate so both inputs are 0 and the output is 1. Finally we remove the pulse that started it all. By removing the pulse we are simply returning the signal at input A to its prior state. Notice the even though input A returns to 1 the outputs remain in their new state because the positive feedback from the upper gate forces the circuit to remain in the state Q 0 and Q 1. It should be apparent to you that we could repeat the process with a negative going pulse on input B and the outputs would flip back to their original state. You should be able to repeat the analysis of the NAND gate in Figure with the NOR gate. In this case it is a positive going pulse that initiates the state transition rather than a negative pulse. Flip-Flops If we apply a second negative pulse to input A of the NAND gate of Figure the system remains unchanged because the output of the upper NAND gate is still 0. The only way to SET the circuit to the way it was is to provide a negative pulse at input B. Thus we can see that 1 input is the SET input setting Q 1 and the other input is the RESET input setting Q 0 . This type of circuit element is called a flip-flop because the two outputs flip and flop back and forth like a playground teeter-totter. This particular type of flip-flop is an RS flip-flop because the two inputs alternately reset R or
