Hardware Acceleration of EDA Algorithms- P5: Single-threaded software applications have ceased to see significant gains in performance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a significant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, field-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose singlethreaded CPU | References 59 inter-bank communication. By implementing these using fast board-level IO the system of cooperating SAT ICs can be made to operate extremely fast. The decision engine of each IC other than the root IC behaves as a communication unit in such a scenario. Chapter Summary In this chapter we have presented a custom IC implementation of a hardware SAT solver and also augmented it for extracting the minimum unsatisfiable core. The speed and capacity for our SAT solver obtained are dramatically higher than those reported for existing hardware SAT engines. The speedup comes from performing the tasks of computing implications and determining conflicts in parallel using a specially designed clause cell. Approaches to partition a SAT instance into banks and bin them into strips have been developed resulting in a very high utilization of clause cells. Also through SPICE simulations we determined that the average power consumed per cycle by our SAT solver is under 1 mW which further strengthens the practicality of our approach. Note that although we used a variant of the BCP engine of GRASP 28 in our hardware SAT solver the hardware approach can be modified to implement other BCP engines as well. For extracting the unsatisfiable core we implemented the approach described in 19 since our architecture naturally complements the technique proposed in 19 . Also the additional optimizations of 19 can be seamlessly implemented in our architecture. References 1. ftp pub challenge satisfiability . The DIMACS ftp site 2. http cs research formalmethods minisat . The MiniSAT Page 3. http simon contest04 results . The SAT 04 Competition 4. Abramovici M. Saab D. Satisfiability on reconfigurable hardware. In Proceedings International Workshop on Field Programmable Logic and Applications pp. 448-456 1997 5. Abramovici M. de Sousa J. Saab D. A massively-parallel easily-scalable satisfiability solver using reconfigurable
