Hardware Acceleration of EDA Algorithms- P11: Single-threaded software applications have ceased to see significant gains in performance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a significant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, field-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose singlethreaded CPU | 12 Conclusions 185 L2 Cache Fig. Larrabee architecture from Intel multiprocessor SM . The block diagram of a single SM is shown in Fig. and the block diagram of a core within an SM is shown in Fig. . With these upcoming architectures newer approaches for hardware acceleration of algorithms would become viable. These approaches could exploit the more general computing paradigm offered by the newer architectures. For example the close coupling between the GPU and the CPU which reside on the same die would 186 12 Conclusions Instruction Cache Scheduler Scheduler Dispatch Dispatch Register File Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Load Store Units X 16 I Special Func Units X 4 I Interconnect Network 64K Configurable Cache Shared Mem Uniform Cache Fig. Block diagram of a single shared multiprocessor SM in Fermi reduce the communication cost. Also in these upcoming architectures the instruction dispatch unit is distributed and the instruction set is more general purpose. These enhancements would enable a more general computing paradigm in comparison to the SIMD paradigm for current GPUs which in turn would enable acceleration opportunities for more EDA applications. The approaches presented in this monograph collectively aim to contribute toward enabling the CAD community to accelerate EDA algorithms on modern hardware platforms. Our work demonstrates techniques to rearchitect several EDA algorithms to maximally harness their performance on the alternative platforms under consideration. References 187 CUDA Core Fig. Block diagram of a single processor core in SM References 1. http cs research formalmethods minisat . The MiniSAT Page 2. NVIDIA Tesla GPU Computing Processor. http object IO_ 3. OmegaSim Mixed-Signal Fast-SPICE Simulator. http 4.
