High Level Synthesis: from Algorithm to Digital Circuit- P15: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 7 All-in-C Behavioral Synthesis and Verification with CyberWorkBench 127 3. K. Wakabayashi and T Okamoto C-Based SoC Design Flow and EDA Tools An ASIC and System Vendor Perspective IEEE Trans. Comput. Aided Design Integr. Syst. Vol. 19 No. 12 pp. 1507-1522 2000 4. N. Kobayashi K. Wakabayashi H. Tanaka N. Shinohara T Kanoh Design Experiences with High-Level Synthesis System Cyber I and Behavioral Description Language BDL Proceedings of Asia-Pacific Conference on Hardware Description Languages Oct. 1994 5. Y. Nakamura K. Hosokawa I. Kuroda K. Yoshikawa T Yoshimura A Fast Hardware Soft-ware Co-Verification Method for System-On-a-Chip by Using a C C Simulator and FPGA Emulator with Shared Register Communication pp. 299-304 DAC 2004 6. K. Wakabayashi Unified Representation for Speculative Scheduling Generalized Condition Vector IEICE Trans. Fundamentals Vol. E89-A VLSI Design and CAD Algorithm pp. 34083415 2006 7. Xtensa http 8. Mep http english 9. S. Torii S. Suzuki H. Tomonaga T Tokue J. Sakai N. Suzuki K. Murakami T Hiraga K. Shigemoto Y. Tatebe E. Ohbuchi N. Kayama M. Edahiro T. Kusano N. Nishi A 600 MIPS 120 mW 70pA Leakage Triple-CPU Mobile Application Processor Chip pp. 136-137 ISSCC 2005 Chapter 8 Bluespec A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions Rishiyur S. Nikhil Abstract Bluespec SystemVerilog BSV provides an approach to high-level synthesis that is general-purpose. That is it is widely applicable across the spectrum of data- and control-oriented blocks found in modern SoCs. BSV is explicitly parallel and based on atomic transactions the best-known tool for specifying complex concurrent behavior which is so prevalent in SoCs. BSV s atomic transactions encompass communication protocols across module boundaries enabling robust scaling to large systems and robust IP reuse. The timing model is smoothly refinable from initial coarse functional models to final production designs. A .
