Model-Based Design for Embedded Systems- P76: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 736 Index System-in-FPGA SIF architecture 352 System-level models application model 126 execution platform model 127-129 illustration 126 memory and power model 129-130 performance analysis analytic techniques 6 design space exploration cycle 4-5 distributed embedded platforms 4 picture-in-picture PiP application 7-9 simulation-based methods 5-6 task mapping 129 System-on-chip SoC ANNABELLE average power consumption 338 heterogeneous 336-338 partial dynamic reconfiguration 339 reference locality 338-339 integrated multi-technology systems 603-604 MONTIUM average power consumption 338 design methodology 335-336 heterogeneous 336-338 partial dynamic reconfiguration 339 reconfigurable processing core 333-335 reference locality 338-339 MPSoC programming models models 238 primitives 239 programming levels 238 multiprocessor system 331-333 platform progrmming models advantages and drawbacks 182-184 classes 182 explicit capture of parallelism 184 SiP design process 606 610-611 SystemC AMS extensions architecture level 591-592 cases 591-592 code 598-599 methodology-specific support 595-596 open SystemC initiative OSCI 588-591 refinement activities 592 594 SystemC-based performance analysis distributed embedded systems analytical approaches 29-30 hybrid approaches 31-32 simulative approaches 30-31 experimental results 47-50 hybrid approach advantages and disadvantages 35-36 basic block pipeline modelling 40-43 dynamic correction 43-45 software tasks 46-47 static cycle calculation 40 SystemC code annotation 38-40 task switches 46 WCET BCET value 36-38 outlook 50 transaction-level modeling TLM abstraction levels 32 accuracy and speed trade-off 33-34 SystemC-H design environment 297 Systems in package SiP 604 606 610-611 T Tagged signal model TSM 463 Task transaction level interface TTL APIs abstraction levels 240 HW-SW component integration 210 stream processing applications 239 TDL see Timing definition language TDL Tilera processor design methodology 347 features 346 iMesh
