Handbook of Algorithms for Physical Design Automation part 28 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 252 Handbook of Algorithms for Physical Design Automation Suppose these modules are separated by a horizontal cut . heights must be added and widths must be maxed . The width distribution list of the new rectangle is 3 .18 4 .02 5 .5 6 .3 and its height list is 9 .2 10 .5 11 .3 . Repeating this process as the area evaluation algorithm traverses the slicing tree in a bottom-up fashion finally results in distribution lists for chip height and width. The authors use these quantities to compute a cost function that is the combination of expected area and standard deviation of area. Including standard deviation in the cost function makes it more likely that the area of the floorplan obtained by statistical floorplanning is close to the area of the final solution . after module dimensions have all been finalized relative to minimizing expected area alone. The paper also considers a combined height width distribution list . 4 5 .3 6 3 .7 means that a module has height 4 and width 5 with a probability of .3 and a height of 6 and a width of 3 with probability of .7 . This is a more realistic formulation but experimental results have been more promising with the separate distribution lists. FLOORPLANNING FOR MANUFACTURABILITY Floorplanning as we have defined it so far is concerned with the arrangement of components within a single chip. In this section we discuss a floorplanning-like problem that arises because of the economics associated with manufacturing a chip. Recall that several chips can be manufactured from a single wafer. To do this a mask set has to be prepared for the wafer. The cost of creating a mask set is substantial. For high-volume manufacturing . when many chips of the same type are to be produced this one-time cost X is amortized over the number of chips c produced. For low-volume manufacturing few chips have to be produced the cost per chip X c becomes prohibitive. The multiple project reticle concept addresses this problem for low-volume
