Handbook of Algorithms for Physical Design Automation part 30 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 171 Handbook of Algorithms for Physical Design Automation 42. H. Xiang X. Tang and . Wong. An algorithm for integrated pin assignment and buffer planning. ACM Transactions on Design Automation of Electronic Systems TODAES 10 3 561-572 2005. 43. P Hauge R. Nair and E. Yoffa. Circuit placement for predictable performance. In ICCAD 87 Proceedings of the International Conference on Computer-Aided Design 1987 pp. 88-91. ACM Press NY 1987. 44. P Hauge R. Nair and E. Yoffa. Circuit Placement for Predictable Performance. IBM Thomas J. Watson Research Center Yorktown Heights NY 1987. 45. J. Hu and S. Sapatnekar. A survey on multi-net global routing for integrated circuits. Integration The VLSI Journal 31 1 1-49 November 2001. 46. C. Lee. An algorithm for path connections and its applications. IRE Transactions on Electronic Computers EC-10 346-365 September 1961. 47. L. John C. Cheng and T. Lin. Simultaneous routing and buffer insertion for high performance interconnect. In GLSVLSI 96 Proceedings of the 6th Great Lakes Symposium on VLSI p. 148. Washington DC IEEE Computer Society 1996. 48. M. Kang W. Dai T. Dillinger and D. LaPotin. Delay bounded buffered tree construction for timing driven floorplanning. In ICCAD 97 Proceedings of the 1997 IEEE ACM International Conference on Computer-Aided Design pp. 707-712. IEEE Press Piscataway NJ 1997. 49. J. Cong and X. Yuan. Routing tree construction under fixed buffer locations. In DAC 00 Proceedings of the 37th Conference on Design Automation pp. 379-384. ACM Press New York 2000. 50. F. Dragan A. Kahng I. Mandoiu S. Muddu and A. Zelikovsky. Provably good global buffering by multiterminal multicommodity flow approximation. In ASP-DAC 01 Proceedings of the 2001 Conference on Asia South Pacific Design Automation pp. 120-125. ACM Press New York 2001. 51. C. Alpert M. Hrkic J. Hu A. Kahng J. Lillis B. Liu S. Quay S. Sapatnekar A. Sullivan and P Villarrubia. Buffered Steiner trees for difficult instances. In ISPD 01 Proceedings of .
