Handbook of Algorithms for Physical Design Automation part 85 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 822 Handbook of Algorithms for Physical Design Automation FIGURE FIGURE FIGURE Inverter processing. Cell expansion. FIGURE Shattering. cells generally present lower pin capacitances and so may improve the delay on a timing-critical net though it could hurt the delay for another path. The timing analyzer and the optimization metric is the arbiter on whether the optimization suggestion is accepted by PDS. When correcting hold violations short paths the off-path cells can be powered up to present higher pin capacitance and slow down a path. Shattering Similar to cell expansion larger fan-in cell can be decomposed into a tree of smaller cells. This may allow the most critical path to move ahead to a faster smaller cell. Figure shows how the delay through pins A and B of a five-input AND gate can be reduced by shattering the gate into three NAND gates so that a and b only need to propagate through a cell with less complexity. Merging the opposite of shattering can also be an effective timing optimization. A rule of thumb is that merging is good when the slacks at the inputs of a tree are similar and shattering is good when there is a wider distribution of slacks. Placement-Driven Synthesis Design Closure Tool 823 Note that the optimizations are atomic actions and are synergistic. Optimizations can call other optimizations. For example a box could be shattered then pin-swapped and finally resized and the new solution could then be accepted or rejected based on the combined effect of these optimizations. Advanced Synthesis Techniques The descriptions of some of the above incremental synthesis optimizations are deceptively simple. For example Figure shows an XOR decomposed as two inverters and three NAND gates. It could also be implemented as two inverters two ANDs and an OR two inverters one OR and two NANDs or three inverters an AND and two NANDs etc. An optimization like cell expansion examines several decompositions based on rules .
