Handbook of Algorithms for Physical Design Automation part 94 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 912 Handbook of Algorithms for Physical Design Automation 3. S. Rusu. Clock generation and distribution for high-performance processors. In IEEE Intl. SOC Conf. Santa Clara CA p. 207 2004. 4. C. F. Webb et al. A 400-MHz S 390 microprocessor. IEEE J. Solid-State Circuits 32 11 1665-1675 November 1997. ISSCC 1997 . 5. P J. Restle et al. The clock distribution of the Power4 microprocessor. In Proc. IEEE Intl. Solid-State Circuits Conf. San Francisco CA pp. 144-145 2002. 6. D. W. Bailey and B. J. Benschneider. Clocking design and analysis for a 600-MHz Alpha microprocessor. IEEE J. Solid-State Circuits 33 11 1627-1633 November 1998. ISSCC 1998 . 7. I. A. Young M. F. Mar and B. Bhushan. A pm CMOS 3-880MHz PLL N 2 clock multiplier and distribution network with low jitter for microprocessors. In Proc. IEEE Intl. Solid-State Circuits Conf. San Francisco CA pp. 330-331 1997. 8. R. Senthinathan S. Fischer H. Rangchi and H. Yazdanmehr. A 650-MHz IA-32 microprocessor with enhanced data streaming for graphics and video. IEEE J. Solid-State Circuits 34 11 1454-1465 November 1999. Microprocessor Report 1999 . 9. N. Kurd J. Barkatullah and R. Dizon. A multigigahertz clocking scheme for the Pentium 4 microprocessor. IEEE J. Solid-State Circuits 36 11 1647-1653 November 2001. ISSCC 01 . 10. N. Bindal et al. Scalable sub-10ps skew global clock distribution for a 90 nm multi-GHz IA microprocessor. In Proc. IEEE Intl. Solid-State Circuits Conf. San Francisco CA pp. 346-498 2003. 11. S. Tam et al. Clock generation and distribution for the first IA-64 microprocessor. IEEE J. Solid-State Circuits 35 11 1545-1552 2000. ISPD 2000 . 12. F. E. Anderson J. S. Wells and E. Z. Berta. The core clock system on the next generation Itanium microprocessor. In Proc. IEEE Intl. Solid-State Circuits Conf. San Francisco CA pp. 146-147 2002. 13. S. Tam R. D. Limaye andU. N. Desai. Clock generation and distribution for the 130-nm Itanium 2 processor with 6-MB on-die L3 cache. IEEE J. Solid-State .
