Để các chi tiết trên mặt nạ, trên phiến silicon của lần chế tạo trước đó (với một mặt khác trong cả bộ) trùng khít lên những chi tiết của mặt nạ hiện tại người ta phải dùng một kỹ thuật gọi là kỹ thuật đồng chỉnh (so mask hay mask aligner). Kỹ thuật này được thực hiện thông qua những dấu hiệu gọi là dấu so (mask marks) với sự trợ giúp quang học (kính hiển vi, CCD camêra ) và hệ vi chỉnh cơ khí theo các chiều X,Y và chỉnh méo. . | Computer Design Rule Checks Pũlysiiicon Polysihcon FIGURE Transistor source width. If a designer creates or changes a geometrical specification file manually a design rule check DRC is required. Because of the large number of geometries and the wide variation in number and style of geometrical design rules in today s circuits computer-based DRCs are necessary. Two different styles of DRC programs arc in wide use. These can be categorized as polygonal checks and raster scan checks. Both styles will be described briefly. Polygonal design rule checks are widely used witbin the semiconductor industry. The geometrical specification file is expanded to produce polygons defining all connected areas for the layer s of interest. Note that the layer of interest may be a composite area such as active transistor area or perhaps depletion transistor area. Or it may be a difference area such as the ion implantation overhang created by subtracting the depletion transistor area from the ion implan- Drain Apparent diffusion diffusion Source diffusion đ Source Drain diffusion Apparent diffusion Source tat ion area. These special areas can be defined by logical operations on primitive layers. Once the polygonal definitions are formed they can be analyzed for width and spacing errors. One valuable feature of encircling a connected area with a single polygon is that electrical connectivity Information is immediately available. Polygonal design rule checks require substantial computing resources because of the many mathematical operations that must be performed during the check. Design rule checks can also be performed in a relatively simple way as raster scan checks by passing small filters over a rasterized image of the integrated circuit. To allow this an entire geometrical specification file is instantiated expanded into the geometries and layers that represent the layout within a twodimensional array where the dimensions represent the A and y coordinates of a point and the .
