Certified that the work contained in the thesis entiled " Verilog-to-C-Compiler: Simulator Generator " by " Anand Vivek Srivastava", has been carried out under my supervision and that this work has not been submitted elsewhere for a degree. This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization. Busses of up to 32 or 64 bits can be modeled as C integers. | Verilog-to-C-Compiler Simulator Generator A Thesis Submitted in Partial Fulfilment of the Requirements for the Degree of Master of Technology by Anand Vivek Srivastava to the DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY KANPUR January 2007 CERTIFICATE Certified that the work contained in the thesis entitled Verilog-to-C-Compiler Simulator Generator by Anand Vivek Srivastava has been carried out under my supervision and that this work has not been submitted elsewhere for a degree. Prof. Raj at Moona Professor Department of Computer Science and Engineering Indian Institute of Technology Kanpur. January 2007 ii Contents List of Tables vi 1 Introduction 1 Objective . 1 Motivation. 2 Survey of Related Works. 2 Verilator. 3 vl2mv. 3 Carbonized RTL Machine Objects. 4 Overview. 4 Organization of the Report. 5 2 Verilog-to-C-compiler Design 6 Front end. 7 Lexical Analyzer. 7 Syntactic Parser. 7 Semantic Analyzer. 7 Optimizers. 8 Parameter replacement. 8 Constant Folding. 8 Dead code removal. 9 Back end Code generator. 10 Modules and Module Instantiations. 11 Variable Declarations. 12 .
