Ngôn ngữ mô tả phần cứng verilog

Tài liệu tham khảo Ngôn ngữ mô tả phần cứng verilog bằng tiếng anh | Following is the Verilog code for flip-flop with a positive-edge clock. module flop elk d q input elk d output q reg q always @ posedge elk begin q d end endmodule Following is Verilog code for a flip-flop with a negative-edge clock and asynchronous clear. module flop elk d clr q input elk d clr output q reg q always @ negedge elk or posedge clr begin if clr q 1 bO else q d end endmodule Following is Verilog code for the flip-flop with a positive-edge clock and synchronous set. module flop elk d s q input elk d s output q reg q always @ posedge elk begin if 3 q l bl else q d end endmodule Following is Verilog code for the flip-flop with a positive-edge clock and clock enable. module flop elk d ce q input elk d ce output q reg q always @ posedge elk begin if ce q d end endmodule Following is Verilog code for a 4-bit register with a positive-edge clock asynchronous set and clock enable. module flop elk d ce pre q input elk ce pre input 3 0 d output 3 0 q reg 3 0 q always @ posedge elk or posedge pre begin if pre q 4 bull else if ce q d end endmodule Following is the Verilog code for a latch with a positive gate module latch g d q input g droutput q reg q always @ g or d begin if g q drend endmodule Following is the Verilog code for a latch with a positive gate and an asynchronous clear. module latch g d clr q - input g d clr output q reg q always @ g or d or clr begin if clr q 1 bO else if g q d end endmodule Following is Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset. module latch g d pre q input g pre input 3 0 d output 3 0 q reg 3 0 q always @ g or d or pre begin if pre q 4 bull else if g q d end endmodule Following is Verilog code for a tristate element using a combinatorial process and always block. module three_st t i o input t i output o reg o always @ t or i begin if t o i else o 1 bZ end endmodule Following is the Verilog code for a tristate element using a concurrent assignment. module three_st t i o input t i output o .