What is the correct schematic for the pullup circuitry? Assuming the pullup circuitry is designed correctly, what is the logic function implemented this gate? Assuming the pullup circuitry is designed correctly, when the output of the CMOS gate above is a logic "0", in the steady state what would we expect the voltage of the output terminal to be? What would be the voltage if the output were a logic "1"? | MIT OpenCourseWare http Computation Structures Spring 2009 For information about citing these materials or our Terms of Use visit http terms. CMOS technology Problem 1. The following diagram shows a schematic for the pulldown circuitry for a particular CMOS gate A. What is the correct schematic for the pullup circuitry B. Assuming the pullup circuitry is designed correctly what is the logic function implemented this gate C. Assuming the pullup circuitry is designed correctly when the output of the CMOS gate above is a logic 0 in the steady state what would we expect the voltage of the output terminal to be What would be the voltage if the output were a logic 1 Problem 2. The following diagram shows a schematic for the pullup circuitry for a particular CMOS gate A. Draw a schematic for the pulldown circuitry for this CMOS gate. B. Assuming the pulldown circuitry is designed correctly give an expression for the logic function implemented by this gate. Problem 3. Consider the following circuit built from nfets and pfets A. Can this circuit be used as a CMOS gate If not explain why. If so what function does it compute B. If we wanted the output voltage to change more quickly when going from a logic 0 to a logic 1 what changes would we make to the fets Problem 4. Consider the 4-input Boolean function Y A B C D where is AND and is OR. A. Implement the function with a single 4-input CMOS gate and an inverter. Problem 5. Anna Logue a circuit designer who missed several early lectures is struggling to design her first CMOS logic gate. She has implemented the following circuit
