For getting points in any question, you will have to simulate the testbenches and show us the waveform files for each question on Sunday, 14th May, at 10:30 AM, in the VLSI Lab. | EE Summer Camp - 2006 Verilog Lab Objective Simulation of basic building blocks of digital circuits in Verilog using ModelSim simulator Points to be kept in mind For getting points in any question you will have to simulate the testbenches and show us the waveform files for each question on Sunday 14th May at 10 30 AM in the VLSI Lab. Consultation is allowed for questions 1 and 3 amongst students. Consultation for questions 2 4 and 5 is only allowed with us. Please do not attempt to copy from each other or from internet. We would very much like to personally clear any doubts that you have just mail us. It would be highly beneficial to consult your digital electronics textbooks like Taub Scilling. 1. Learn use of ModelSim simulator by writing the Verilog code to simulate a half adder where a b are 1-bit inputs and sum carry are 1-bit outputs. A sample code and its associated test bench is given below. 4 points module halfadder a b sum carry input a b output sum carry wire sum carry assign sum aAb sum bit assign carry a b carry bit endmodule module main reg a b wire sum carry halfadder add a b sum carry always @ sum or carry begin display time d b b b carry b n time a b sum carry end initial begin a 0 b 0 5 a 0 b 1 5 a 1 b 0 5 a 1 b 1 end endmodule 2. Write the verilog code for a Full Adder that takes in three 1-bit inputs a b and carryin and gives sum and carryout 1-bit outputs. Write the code for a testbench for the adder and give appropriate inputs to test all possible combinations. 6 points 1 3. Simulate the code for the D flipflop discussed in class and given below. 4 points define TICK 2 Flip-flop delay module dflipflop d clk reset q input d clk reset output q reg q always @ posedge clk or posedge reset begin if reset begin q 0 end else begin q TICK d end end endmodule module main reg d clk rst wire q dflipflop dff d clk rst q Always at rising edge of clock display the signals always @ posedge clk begin display d b clk b rst b q b n d clk rst q end Module to .
