Tuyến tính (tuần tự) giải quyết. Mục tiêu gia tăng địa chỉ bằng 4 sau mỗi giai đoạn dữ liệu. PM. Mục tiêu ngắt kết nối sau giai đoạn dữ liệu đầu tiên. Bọc đường bộ nhớ cache. Mới trong Rev . Nếu địa chỉ ban đầu không phải là bắt đầu của dòng bộ nhớ cache, bọc xung quanh cho đến khi bộ nhớ cache dòng đầy. PM. Mục tiêu ngắt kết nối sau giai đoạn dữ liệu đầu tiên. | PCI Bus Demystified Table 3-2 AD1 AD0 Address Sequence 0 0 Linear sequential addressing. Target increments address by 4 after each data phase. 0 1 Reserved. Target disconnects after first data phase. 1 0 Cache line wrap. New in Rev. . If initial address was not beginning of cache line wrap around until cache line filled. 1 1 Reserved. Target disconnects after first data phase. Cache line wrap mode only applies if a burst begins in the middle of a cache line. When the end of the cache line is reached the address wraps around to the beginning of the cache line until the entire line has been transferred. If the burst continues beyond this point the next transfer is to from the same location in the next cache line where the transfer began. Here s an example Consider a cache line size of 16 bytes 4 DWORDs and a transfer that begins at location 8. The first transfer is to location 8 the second to location C hex which is the end of the cache line. The third data phase is to address 0 and the fourth to address 4. If the burst continues the next data phase will be to location 18 hex. Targets are not required to support cache line wrap. If a target does not support this feature it should terminate the transaction after the first data phase. Addresses for transfers to I O space are fully qualified to the byte level. That is AD 1 0 convey valid address information inferring the 38 Bus Protocol least significant valid byte. This in turn implies which C BE signals are valid. Thus for example if AD 1 0 00 at a minimum C BE 0 must be 0 to transfer the low-order byte but up to four bytes could be transferred. Conversely if AD 1 0 11 only the high-order byte can be transferred so C BE 3 is 0 and C BE 2 0 must be 1. See Table 3-3. Table 3-3 AD1 0 implies which BE lines are valid AD1 AD0 C BE 3 C BE 2 C BE 1 C BE 0 0 0 X X X 0 0 1 X X 0 1 1 0 X 0 1 1 1 1 0 1 1 1 0 line must be asserted 1 line must not be asserted X line may be asserted DEVSEL Timing The selected target is required
