Nếu nổ vẫn tiếp tục vượt quá điểm này, việc chuyển nhượng tiếp theo là đến / từ cùng một vị trí trong dòng bộ nhớ cache tiếp theo hợp chuyển nhượng bắt đầu. Dưới đây là một ví dụ: Hãy xem xét một kích thước bộ nhớ cache của dòng 16 byte (4 DWORDs) và chuyển giao bắt đầu tại vị trí 8. Việc chuyển giao đầu tiên là vị trí 8, thứ hai để hex vị trí C là sự kết thúc của dòng bộ nhớ cache | PCI Bus Demystified 3. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. The specified load Figure 5-5 is optional . the designer may elect to meet this parameter with an unloaded output per revision of the PCI Local Bus Specification. However adherence to both maximum and minimum parameters is now required the maximum is no longer simply a guideline . Since adherence to the maximum slew rate was not required prior to revision of the specification there may be components in the market for some time that have faster edge rates therefore motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. Equation D Equaliun C 59ft Figure 5-6 Characteristic V I curves for a PCI driver in the V signaling environment. 80 Electrical and Mechanical Issues Timing Specifications Clock Figure 5-7 shows the clock waveform and the required measurement points. Table 5-5 summarizes the specifications. For expansion boards clock measurements are made at the expansion board PCI component and not at the connector. Note again the distinction between the 5 V and V signaling environments. Figure 5-7 Clock waveform and required measurement points. Table 5-5 Clock and reset specifications. Symbol Parameter Min Max Units Notes Tcyc CLK Cycle Time 30 tt ns 1 Thigh CLK High Time 11 ns T low CLK Low Time 11 ns CLK Slew Rate 1 4 V ns 2 RST Slew Rate 50 MV ns 3 81 PCI Bus Demystified Notes for Table 5-5 1. In general all PCI components must work with any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system so long as
