Cấu hình phần mềm ghi kích thước bộ nhớ cache hệ thống đường trong gia DWORD đăng ký này. Nó là cần thiết cho bất kỳ chủ mà thực hiện bộ nhớ Viết và mất hiệu lực của lệnh và cho bất kỳ mục tiêu mà thực hiện bộ nhớ cache-line bọc giải quyết. Thạc sĩ thực hiện các lệnh đọc tiên tiến nên tận dụng lợi thế của các đăng ký này để tối ưu hóa sử dụng các lệnh đọc. Cardbus CIS Pointer. | C H A P T E R 8 PCI Bridging The notion of bridging plays a significant role in PCI architecture primarily due to electrical limitations that impose a severe limit on the number of devices residing on a single PCI bus segment. In some cases it is also desirable to functionally isolate portions of the system so they can operate in parallel. Bridge Types In this chapter we re primarily concerned with the PCI-to-PCI P2P bridge that is a bridge that connects two PCI bus segments. The P2P bridge is defined in PCI-to-PCI Bridge Architecture Specification Rev. December 1998. But before delving into the details of the P2P bridge we should note briefly that there are two other types of bridges that serve specific roles as illustrated in Figure 8-1. Host-to-PCI Bridge None of today s popular processor architectures has a PCI bus coming directly off the chip. Rather each processor defines its own local bus optimized around the specific architecture. External cache and main memory often reside on the local processor bus. Some local busses also support multiple processors. 125 PCI Bus Demystified Figure 8-1 PCI bridge hierarchy. The Host-to-PCI bridge provides the translation from the local processor bus to the PCI. In conventional PC environments the Host-to-PCI bridge often referred to as the North Bridge is one element of the chipset and is usually contained in the same chip that manages main memory and the Level 2 cache. To the extent feasible the architecture of the Host-to-PCI bridge mimics the P2P bridge specification. PCI-to-Legacy Bus Bridge Someday the ISA bus will disappear from PC architecture. Someday income tax forms will be understandable. But for the time being legacy busses such as ISA and EISA are supported through the mechanism of a PCI-to-Legacy Bridge. Like the Host-to-PCI bridge this is usually an element of the chipset that also incorporates such traditional features as IDE interrupt and DMA controllers. Legacy bridges often implement subtractive .
