Tùy chọn. Thực hiện bởi các thiết bị silicon chia sẻ giữa các thiết bị CardBus và PCI. Nó chỉ đến cấu trúc thông tin thẻ để thực hiện Cardbus. Thông tin chi tiết của CIS có thể được tìm thấy trong sửa đổi của đặc tả PC Card. Khả năng | PCI Bridging Clock 2 The master deasserts LOCK during the address phase. This is how the locked target knows its being accessed by the master owning the lock. Only the device asserting LOCK can release it. 3 and 4 The transaction proceeds normally. 5 If this is the last transaction in the locked series the master releases LOCK . CLK FRAME LOCK AD IRDY TRDY 1 2 3 4 5 Release Continue Target unlocks when it detects FRAME and LOCK deasserted Figure 8-16 Subsequent lock transactions. If a locked target sees LOCK asserted during the address phase a master other than the one owning the lock is attempting to access the locked target Figure 8-17 . In this case the target executes a retry abort. 145 PCI Bus Demystified CLK FRAME LOCK AD IRDY TRDY STOP DEVSEL 1 2 3 4 5 I I I Asserted by master holding j lock -J Addrệss Figure 8-17 Accessing a locked target. Summary Bridging is the mechanism that allows a PCI system to expand beyond the electrical limits of a single bus segment. Bridges also serve to interface the host processor to PCI host-to-PCI bridge and to interface PCI to legacy busses PCI-to-ISA bridge . Once configured the primary job of a PCI-to-PCI bridge is to act as an address filter accepting transactions directed at agents downstream of it and ignoring transactions that fall outside of its address windows. Bridges are allowed to prefetch read data and post write data provided they observe rules to prevent deadlocks and avoid reading stale data. Write posting can create a problem for interrupts because the interrupt may arrive at the host processor before the associated 146 PCI Bridging data buffer is written to memory. The Message Signaled Interrupt capability solves this problem by treating interrupts as bus transactions rather than as separate signals. The interrupt transactions are subject to the same ordering rules as data transfers so that things happen in the right order. Under rare circumstances a master is allowed to lock a target for exclusive access. .
