Phần này chỉ áp dụng đối với các PIC18F4X2 thiết bị. Porte là một 3-bit, cổng bi-directional. Hướng đăng ký dữ liệu tương ứng là TRISE. Thiết lập một chút TRISE (= 1) sẽ làm cho các pin Porte tương ứng với một đầu vào (tức là đặt các trình điều khiển đầu ra tương ứng trong một chế độ Hi-Trở kháng). | PIC18FXX2 PORTE TRISE and LATE Registers This section is only applicable to the PIC18F4X2 devices. PORTE is a 3-bit wide bi-directional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit 1 will make the corresponding PORTE pin an input . put the corresponding output driver in a Hi-Impedance mode . Clearing a TRISE bit 0 will make the corresponding PORTE pin an output . put the contents of the output latch on the selected pin . The Data Latch register LATE is also memory mapped. Read-modify-write operations on the LATE register reads and writes the latched output value for PORTE. PORTE has three pins RE0 RD AN5 RE1 WR AN6 and RE2 CS AN7 which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. Register 9-1 shows the TRISE register which also controls the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When selected as an analog input these pins will read as 0 s. TRISE controls the direction of the RE pins even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note On a Power-on Reset these pins are configured as analog inputs. PORTE BLOCK DIAGRAM IN I O PORT MODE FIGURE 9-9 1 Note 1 I O pins have diode protection to Vdd and Vss. EXAMPLE 9-5 INITIALIZING PORTE CLRF PORTE Initialize PORTE by clearing output data latches CLRF LATE Alternate method to clear output data latches MOVLW 0x07 Configure A D MOVWF ADCON1 for digital inputs MOVLW 0x05 Value used to initialize data direction MOVWF TRISE Set RE 0 as inputs RE 1 as outputs RE 2 as inputs 2006 Microchip Technology Inc. DS39564C-page 97 PIC18FXX2 REGISTER 9-1 TRISE REGISTER R-0 R-0 R W-0 R W-0 U-0 R W-1 R W-1 R W-1 IBF I OBF I IBOV I PSPMODE I I TRISE2 I TRISE1 I TRISE0 bit 7 bit 0 bit 7 IBF Input Buffer Full Status bit 1 A word has been received and waiting to be read by the CPU 0 No word has been received bit 6 OBF
