Porte có ba chân (RE0/RD/AN5, RE1/WR/AN6 và RE2/CS/AN7) cá nhân được cấu hình như đầu vào hay đầu ra. Những chân này có bộ đệm đầu vào Kích hoạt Schmitt. Đăng ký 9-1 cho thấy đăng ký TRISE, mà còn điều khiển hoạt động nô lệ cổng song song. Porte chân được ghép với đầu vào analog | PIC18FXX2 REGISTER 16-1 TXSTA TRANSMIT STATUS AND CONTROL REGISTER R W-0 R W-0 R W-0 R W-0 U-0 R W-0 R-1 R W-0 CSRC TX9 TXEN SYNC - BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC Clock Source Select bit Asynchronous mode Don t care Synchronous mode 1 Master mode clock generated internally from BRG 0 Slave mode clock from external source bit 6 TX9 9-bit Transmit Enable bit 1 Selects 9-bit transmission 0 Selects 8-bit transmission bit 5 TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled Note SREN CREN overrides TXEN in SYNC mode. bit 4 SYNC USART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 Unimplemented Read as 0 bit 2 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed 0 Low speed Synchronous mode Unused in this mode bit 1 TRMT Transmit Shift Register Status bit 1 TSR empty 0 TSR full bit 0 TX9D 9th bit of Transmit Data Can be Address Data bit or a parity bit. Legend R Readable bit W Writable bit U Unimplemented bit read as 0 - n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS39564C-page 166 2006 Microchip Technology Inc. PIC18FXX2 REGISTER 16-2 RCSTA RECEIVE STATUS AND CONTROL REGISTER R W-0 R W-0 R W-0 R W-0 R W-0 R-0 R-0 R-x SPEN 1 RX9 1 SREN 1 CREN 1 ADDEN 1 FERR 1 OERR 1 RX9D bit 7 bit 0 bit 7 SPEN Serial Port Enable bit 1 Serial port enabled configures RX DT and TX CK pins as serial port pins 0 Serial port disabled bit 6 RX9 9-bit Receive Enable bit 1 Selects 9-bit reception 0 Selects 8-bit reception bit 5 SREN Single Receive Enable bit Asynchronous mode Don t care Synchronous mode - Master 1 Enables single receive 0 Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don t care bit 4 CREN Continuous Receive Enable bit Asynchronous mode 1 Enables receiver 0 Disables receiver Synchronous mode 1 Enables continuous receive until enable bit CREN is cleared CREN overrides SREN 0 Disables continuous receive bit 3 ADDEN Address Detect Enable bit Asynchronous mode 9-bit RX9 1 1
