Examples of VHDL Descriptions phần 1

File này có chứa một lựa chọn các tập tin nguồn VHDL phục vụ để minh họa sự đa dạng và sức mạnh của ngôn ngữ khi được sử dụng để mô tả các loại phần cứng. Các ví dụ bao gồm từ logic tổ hợp đơn giản, được mô tả trong điều khoản của các cổng logic cơ bản, | Examples of VHDL Descriptions AMi Advanced Microelectronics For Industrialists Advanced Electronic Design Automation Examples of VHDL Descriptions Author Ian Elliott of Northumbria University This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic described in terms of basic logic gates to more complex systems such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can be synthesised using current synthesis tools. Use the hierarchical links below to navigate your way through the examples Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic Combinational Logic Exclusive-OR Gate Dataflow style p Exclusive-OR Gate Behavioural style j Exclusive-OR Gate Structural style Miscell aneous Logic Gates Three-input Majority Voter Magnitude Comparator Quad 2-input Nand 74x00 BCD to Seven Segment Decoder 1712 J 1 125 Dual 2-to-4 Decoder Octal Bus Transceiver - I I z I iũuiK-AiùỉtỊíỉ. Quad 2-input OR 8-bit Identity Comparator ----------------------1 Hamming Encoder UniixiLiii lỉ Hamming Decoder 2-to-4 Decoder with Testbench and Configuration Multiplexer 16-to-4 using Selected Signal Assignment Statement Multiplexer 16-to-4 using Conditional Signal Assignment Statement Multiplexer 16-to-4 using if-then-elsif-else Statement M68008 Address Decoder Highest Priority Encoder N-input AND Gate Counters http aoursewxre advefa vhd1 1 of 67 2 3 1 2002 4 1 5 0 1 Examples of VHDL Descriptions Counter using a Conversion Function Generated Binary Up Counter L l Counter using Multiple Wait Statements xK- ie Synchronous Down Counter with Parallel Load Mod-16 Counter using JK Flip-flops Pseudo Random Bit Sequence Generator Universal .