MEMORY, MICROPROCESSOR, and ASIC phần 5

Hình 6,18 cho thấy phí cấp do khớp nối Cc tụ trong dòng-bit. MSB được cảm nhận bằng cách sử dụng các mức tham chiếu của một nửa-VCC, như đã đề cập trước đó. MSB tạo ra các mức tham chiếu cho LSB Vs được định nghĩa là mức tín hiệu tuyệt đối của dữ liệu "11" và "00", mức tín hiệu tuyệt đối của dữ liệu "10" và "01" là một thứ ba của Vs. | Dynamic Random Access Memory 6-15 TABLE Charge-Sharing Restore Scheme MSB Restore Level LS 1 1 Vcc 0 1 3 Vcc _ 2Cb MSB Cb LSB V restore - vcc cb B 0 2 3 Vcc 0 GND FIGURE Charge-coupling sensing. Charge-Coupling Sensing Figure shows the charge in bit-line levels due to coupling capacitor Cc. The MSB is sensed using the reference level of half-Vcc as mentioned earlier. The MSB generates the reference level for LSB Vs is defined as the absolute signal level of data 11 and 00 the absolute signal level of data 10 and 01 is one-third of Vs. Here Vs is directly proportional to the ratio between storage capacitor Cs and bit-line capacitance. In the case of sensing data 11 the initial signal level is Vs. After MSB sensing the bit-line level in Section B is changed for LSB sensing by the MSB through coupling capacitor Cc. The reference bitline in Section B is raised by Vc and the other bit-line is reduced by Vc. For LSB sensing Vc is one-third of Vs due to the coupling capacitor Cc. Using the two-step sensing scheme the 2-bit data in a DRAM cell can be implemented. References 1. Sekiguchi. T. et al. An Experimental 220MHz 1Gb DRAM ISSCC . Papers pp. 252 253 Feb. 1995. 2. Sugibayashi T. et al. A 1Gb DRAM for File Applications ISSCC . Papers pp. 254-255 Feb. 1995. 3. Murotani T. et al. A 4-Level Storage 4Gb DRAM ISSCC Dig. Tech. Papers pp. 74-75 Feb. 1997. 4. Furuyama T. et al. An Experimental 2-bit Cell Storage DRAM for Macrocell or Memory-on-Logic Application IEEE J. Solid-State Circuits vol. 24 no. 2 pp. 388-393 April 1989. 5. Ahlquist . et al. A 16k 384-bit Dynamic RAM IEEE J. Solid-State Circuits vol. SC-11 no. 3 Oct. 1976. 6-16 Memory Microprocessor and ASIC 6. El-Mansy Y et al. Design Parameters ofthe Hi-C SRAM cell IEEE J. Solid-State Circuits vol. SC-17 no. 5 Oct. 1982. 7. Lu . C. Half-VDD Bit-Line Sensing Scheme in CMOS DRAM s IEEE J. Solid-State Circuits vol. SC-19 no. 4 Aug. 1984. 8. Lu N. C. C. Advanced Cell .