MEMORY, MICROPROCESSOR, and ASIC phần 9

Transistor cấp mạch particell tương ứng với nhiều đầu vào của một DCC tioned vào DCCs là các yếu tố đầu vào chính của mạch điện hoặc các nút cổng của thiết bị là một phần của DCC . Các kết quả đầu ra của một Một đa thức áp dụng mức độ n, tất nhiên là bị ràng buộc để tồn tại | 13 Logic Synthesis for Field Programmable Gate Array FPGA Technology Introduction 13-1 John WLockwood FPGA Structures 13 2 Look-up Table LUT -Based CLB PLA-Based CLB Multiplexer-Based CLB Interconnect Logic Synthesis 13 4 Technology Independent Optimization Technology Mapping Look-up Table LUT Synthesis 13 6 Library-Based Mapping Direct Approaches Chortle 13 7 Tree Mapping Algorithm Example Chortle-crf Chortle-d Two-Step Approaches 13 12 First Step Decomposition Second Step Node Elimination MIS-pga 2 A Framework for TLU-Logic Optimization Washington University Conclusion 13-16 Introduction Field Programmable Gate Arrays FPGAs enable rapid development and implementation of complex digital circuits. FPGA devices can be reprogrammed and reused allowing the same hardware to be employed for entirely new designs or for new iterations of the same design. While much of traditional IC logic synthesis methods apply FPGA circuits have special requirements that affect synthesis. The FPGA device consists of a number of configurable logic blocks CLBs interconnected by a routing matrix. Pass transistors are used in the routing matrix to connect segments of metal lines. There are three major types of CLBs those based on PLAs those based on multiplexers and those based on table lookup TLU functions. Automated logic synthesis tools are used to optimize the mapping of the Boolean network to the FPGA device. FPGA synthesis is an extension to the general problem of multi-level logic synthesis. FPGA logic synthesis is usually solved in two phases. The technology-independent phase uses a general multi-level logic optimization tool such as Berkeley s MIS to reduce the complexity of the Boolean network. Next a technology-dependent optimization phase is used to optimize the logic for the particular type of device. In the case of the TLU-based FPGA each CLB can implement an arbitrary logic 0-8493-1737-1 03 2003 by CRC Press LLC 13-1 13-2 .