bắt đầu control_unit: chặn cổng (port danh sách); cổng bản đồ (hiệp hội danh sách); tờ khai control_unit bắt đầu báo cáo cho khối cuối control_unit control_unit; data_path: chặn cổng (port danh sách); cổng bản đồ (hiệp hội danh sách); tờ khai cho data_path bắt đầu báo cáo cho data_path cuối khối data_path, block_structure kết thúc; | 7. Sample Models The DP32 Processor 7-3 Instruction Name Function opcode Ld load r3 M r1 disp32 X 20 St store M r1 disp32 r3 X 21 Ldq load quick r3 M r1 i8 X 30 Stq store quick M r1 i8 r3 X 31 Table7-2. DP32 load and store instructions. Instruction Name Function opcode Br-ivnz branch if cond then PC PC disp32 X 40 Brq-ivnz branch quick if cond then PC PC i8 X 51 Bi-ivnz branch indexed if cond then PC r1 disp32 X 41 Biq-ivnz branch indexed quick if cond then PC r1 i8 X 51 Table7-3. DP32 load and store instructions. Finally there are four branch instructions listed in Table7-3 each with a slightly different format. The format of the ordinary brach is 31 24 23 20 19 16 15 8 7 0 Addr op xxxx ivnz xxxx xxxx Addr 1 disp The format of a quick branch is 31 24 23 20 19 16 15 8 7 0 Addr op xxxx ivnz xxxx i8 The format of an indexed branch 31 24 23 20 19 16 15 8 7 0 Addr op xxxx ivnz r1 xxxx Addr 1 disp The format of a quick indexed branch 31 24 23 20 19 16 15 8 7 0 Addr op xxxx ivnz r1 i8 The op field is the op-code disp is a long immediate displacement i8 is a short immediate displacement r1 is used as an index register and ivnz is a the condition mask. The branch is taken if cond V v N n Z z i. 7-4 The VHDL Cookbook DP32 PHI1 FETCH PHI2 READ RESET WRITE READY A_BUS D_BUS Phil Jn-J A-J- phi2 Figure7-3. DP32 clock waveforms. Figure7-2. DP32 port diagram. . Bus Architecture The DP32 processor communicates with its memory over synchronous 32-bit address and data buses. The external ports of the DP32 are shown in Figure7-2. The two clock inputs phil and phi2 provide a two-phase non-overlapping clock for the processor. The clock waveforms are shown in Figure7-3. Each cycle of the phil clock defines a bus state one of Ti idle T1 or T2. Bus transactions consist of a T1 state followed by one or more T2 states with Ti states between transactions. The port a_bus is a 32-bit address bus and d_bus is a 32-bit bidirection data bus. The read and write ports control bus read and write
