Số lượng các chu kỳ thực hiện để thực thi một hướng dẫn nhân phụ thuộc vào việc thực hiện xử lý. Đối với một số triển khai thời gian chu kỳ cũng phụ thuộc vào giá trị trong Rs. Để biết thêm chi tiết về định thời chu kỳ, xem Phụ lục D. Ví dụ Ví dụ này cho thấy một hướng dẫn nhân đơn giản rằng nhân đăng ký r1 và r2 3,11 và đặt kết quả vào đăng ký r0. | 58 Chapter 3 Introduction to the ARM Instruction Set The number of cycles taken to execute a multiply instruction depends on the processor implementation. For some implementations the cycle timing also depends on the value in Rs. For more details on cycle timings see Appendix D. Example This example shows a simple multiply instruction that multiplies registers r1 and r2 together and places the result into register r0. In this example register r1 is equal to the value 2 and r2 is equal to 2. The result 4 is then placed into register r0. PRE r0 0x00000000 r1 0x00000002 r2 0x00000002 MUL r0 r1 r2 r0 r1 r2 POST r0 0x00000004 r1 0x00000002 r2 0x00000002 The long multiply instructions SMLAL SMULL UMLAL and UMULL produce a 64-bit result. The result is too large to fit a single 32-bit register so the result is placed in two registers labeled RdLo and RdHi. RdLo holds the lower 32 bits of the 64-bit result and RdHi holds the higher 32 bits of the 64-bit result. Example shows an example of a long unsigned multiply instruction. Example The instruction multiplies registers r2 and r3 and places the result into register r0 and r1. Register r0 contains the lower 32 bits and register r1 contains the higher 32 bits of the 64-bit result. PRE r0 r1 r2 r3 0x00000000 0x00000000 0xf0000002 0x00000002 UMULL r0 r1 r2 r3 r1 r0 r2 r3 POST r0 0xe0000004 RdLo r1 0x00000001 RdHi Branch Instructions A branch instruction changes the flow of execution or is used to call a routine. This type of instruction allows programs to have subroutines if-then-else structures and loops. Branch Instructions 59 The change of execution flow forces the program counter pc to point to a new address. The ARMv5E instruction set includes four different branch instructions. Syntax B cond label BL cond label BX cond Rm BLX cond label Rm B branch pc label BL branch with link pc label Ir address of the next instruction after the BL BX branch exchange pc Rm 0xfffffffe T Rm 1 BLX branch exchange with
