Analog-to-Digital Converters, Part II Trong phòng thí nghiệm cuối cùng, đếm nhị phân trong các hình thức quầy lên và lên / xuống đã được sử dụng để tạo ra dạng sóng thử nghiệm cho ADCs đoạn đường nối và theo dõi. Một ADC phổ biến là dựa trên một dạng sóng thử nghiệm được tạo ra từ một đăng ký xấp xỉ liên tiếp (SAR). Những ADCs nhanh hơn đáng kể so với ADCs đoạn đường nối và có một thời gian chuyển đổi liên tục và được biết đến. SAR làm cho việc sử dụng của các chương. | Lab 9 Analog-to-Digital Converters Part II In the last lab binary counters in the form of up and up down counters were used to create test waveforms for ramp and tracking ADCs. Another popular ADC is based on a test waveform created from a successive approximation register SAR . These ADCs are substantially faster than the ramp ADCs and have a constant and known conversion time. SARs make use of the binary weighting scheme by outputting each bit in succession from the most significant bit MSB to the least significant bit LSB . The SAR algorithm is as follows 1. Reset the SAR register and set the DAC to zero. 2. Set MSB of SAR if VDAC is greater than Vin then turn that bit off. else if VDAC is less than Vin leave the bit on. 3. Repeat step 2 for the next MSB until all n bits of the SAR have been set and tested. 4. After n cycles the digital output of the SAR will contain the digitized value of the input signal. This algorithm can best be seen with the aid of a graph of the input signal level and the DAC waveform produced by the SAR. Suppose a value of 153 is input into the ADC circuit. The number 153 is 128 16 8 1. In binary reading right to left the number is 15310 10011001 2 The SAR algorithm states that the MSB having the value of 128 is to be tested first. Because 128 is less than 153 the MSB is to be kept. The best estimate after the first cycle is 1000 0000 . On the next cycle the next MSB having value 64 is added to the best estimate that is 128 64 192 . Because 192 is greater than 153 this bit is not kept and the best estimate remains 1000 0000 . In the following cycle the next bit value of 32 yields a test value of 128 32 160. Again the test value is greater than the input National Instruments Corporation 9-1 Fundamentals of Digital Electronics Lab 9 Analog-to-Digital Converters Part II level so this bit is not kept and the best estimate remains at 1000 0000 . In the following cycle the next test value of 16 yields 128 16 144. This value is less than 153 so
