VHDL Programming by Example phần 2

một cách hợp lý các khu vực nhóm của mô hình. Tương tự với một hệ thống nhập Schematic điển hình là một tấm sơ đồ. Trong một hệ thống nhập Schematic điển hình, một mức độ hoặc một phần của thiết kế có thể được đại diện bởi một số tờ sơ đồ mạch. | 32 Chapter Two to logically group areas of the model. The analogy with a typical Schematic Entry system is a schematic sheet. In a typical Schematic Entry system a level or a portion of the design can be represented by a number of schematic sheets. The reason for partitioning the design may relate to C design standards about how many components are allowed on a sheet or it may be a logical grouping that the designer finds more understandable. The same analogy holds true for block statements. The statement area in an architecture can be broken into a number of separate logical areas. For instance if you are designing a CPU one block might be an ALU another a register bank and another a shifter. Each block represents a self-contained area of the model. Each block can declare local signals types constants and so on. Any object that can be declared in the architecture declaration section can be declared in the block declaration section. Following is an example LIBRARY IEEE USE PACKAGE bit32 IS TYPE tw32 IS ARRAY 31 DOWNTO 0 OF std_logic END bit32 LIBRARY IEEE USE USE ENTITY cpu IS PORT clk interrupt IN std_logic addr OUT tw32 data INOUT tw32 END cpu ARCHITECTURE cpu_blk OF cpu IS SIGNAL ibus dbus tw32 BEGIN ALU BLOCK SIGNAL qbus tw32 BEGIN -- alu behavior statements END BLOCK ALU REG8 BLOCK SIGNAL zbus tw32 BEGIN REG1 BLOCK SIGNAL qbus tw32 BEGIN -- reg1 behavioral statements END BLOCK REG1 more REG8 statements Behavioral Modeling 33 END BLOCK REG8 END cpu_blk Entity cpu is the outermost entity declaration of this model. This is not a complete model only a subset. Entity cpu declares four ports that are used as the model interface. Ports elk and interrupt are input ports addr is an output port and data is an inout port. All of these ports are visible to any block declared in an architecture for this entity. The input ports can be read from and the output ports can be assigned values. Signals ibus and dbus .