VHDL Programming by Example phần 8

Một chuyển đăng ký cấp độ mô tả được đặc trưng bởi một phong cách xác định tất cả các của sổ đăng ký trong thiết kế, và logic tổ hợp giữa. Điều này đã được đăng ký và sơ đồ điện toán đám mây trong hình 9-2. Sổ đăng ký được mô tả một cách rõ ràng thông qua thành phần instantiation hoặc ngầm | 332 Chapter Fourteen PACKAGE count_types IS SUBTYPE bits is INTEGER RANGE 0 to 255 END count_types LIBRARY IEEE USE USE ENTITY count IS PORT clk IN std_logic ld IN std_logic up_dwn IN std_logic clk_en IN std_logic din IN bits qout INOUT bits END count ARCHITECTURE synthesis OF count IS SIGNAL count_val bits BEGIN PROCESS ld up_dwn din qout BEGIN IF ld 1 THEN count_val din ELSIF up_dwn 1 THEN IF qout 255 THEN count_val 0 ELSE count_val count_val 1 END IF ELSE IF qout 0 THEN count_val 255 ELSE count_val count_val - 1 END IF END IF END PROCESS PROCESS BEGIN WAIT UNTIL clk EVENT AND clk 1 IF clk_en 1 THEN qout count_val END IF END PROCESS END synthesis Package count_types contains the type declaration for the 8-bit signal type used in the counter. The counter is loadable counts up and down and contains a clock enable. The counter is implemented as two processes a CPU RTL Simulation 333 combinational process and a sequential process. The combinational process calculates the next state of the counter and the sequential process keeps track of the current state of the counter and updates the next state of the counter on a rising edge of the clk input. We use the counter to discuss a number of different types of testbenches. Stimulus Only The stimulus only testbench contains the stimulus driver and DUT blocks of a testbench. The verification process is left to the designer. This type of testbench is useful at the beginning of a design project when no known good vectors exist or for a quick check of an entity. Following is an example stimulus only testbench ENTITY testbench IS END -- STIMULUS ONLY -- testbench for 8-bit loadable counter -- reads from file LIBRARY ieee USE USE USE USE ARCHITECTURE stimonly OF testbench IS -- component declaration for counter COMPONENT count PORT clk IN std_logic ld IN std_logic up_dwn IN std_logic .