Digital design width CPLD Application and VHDL - Chapter 7

Introduction to Sequential Logic Các mạch kỹ thuật số nghiên cứu đến thời điểm này có tất cả các mạch tổ hợp, có nghĩa là, các mạch có kết quả đầu ra là chức năng duy nhất của đầu vào hiện tại của họ. Một tập hợp các đầu vào quốc gia sẽ luôn luôn sản xuất cùng một trạng thái đầu ra trong một mạch tổ hợp. | C H A P T E R iiiiiiiiiii7iiii IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Introduction to Sequential Logic OUTLINE CHAPTER OBJECTIVES Latches NAND NOR Latches Gated Latches Edge-Triggered D Flip-Flops Edge-Triggered JK Flip-Flops Edge-Triggered T Flip-Flops Timing Parameters Upon successful completion of this chapter you will be able to Explain the difference between combinational and sequential circuits. Define the set and reset functions of an SR latch. Draw circuits function tables and timing diagrams of NAND and NOR latches. Explain the effect of each possible input combination to a NAND and a NOR latch including set reset and no change functions as well as the ambiguous or forbidden input condition. Design circuit applications that employ NAND and NOR latches. Describe the use of the ENABLE input of a gated SR or D latch as an en-able inhibit function and as a synchronizing function. Outline the problems involved with using a level-sensitive ENABLE input on a gated SR or D latch. Explain the concept of edge-triggering and why it is an improvement over level-sensitive enabling. Draw circuits function tables and timing diagrams of edge-triggered D JK and T flip-flops. Describe the toggle function of a JK flip-flop and a T flip-flop. Describe the operation of the asynchronous preset and clear functions of D JK and T flip-flops and be able to draw timing diagrams showing their functions. Use MAX PLUS II to create simple circuits and simulations with D latches and D JK and T flip-flops. Create simple flip-flop designs using VHDL. The digital circuits studied to this point have all been combinational circuits that is circuits whose outputs are functions only of their present inputs. A particular set of input states will always produce the same output state in a combinational circuit. 275 .