Logic Design with VHDL | Figure 1-1 Basic Gates AND C AB OR C A B NOT C A EXCLUSIVE OR C A B x Figure 1-2 Full Adder Cin a Full adder module X Y Cin CoutSum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 b Truth Table Sum X Y Cin X YCin XY Cin XYCin X Y Cin Cout X YCin XY Cin XYCin XYCin XY XCin YCin AB CD 00 01 11 10 0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 Figure 1-3 Four-Variable Karnaugh Maps F m 0 2 3 5 6 7 8 10 11 d 14 15 C B D A BD B C D B C D A B
