Tham khảo tài liệu 'bishop, robert h. - the mechatronics handbook [crc press 2002] part 17', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | The time required to finish N instructions in a pipeline with K stages can be calculated. Assume a cycle time of T for the overall instruction completion and an equal T K processing delay at each stage. With a pipeline scheme the first instruction completes the pipeline after T and there will be a new instruction out of the pipeline per stage delay T K. Therefore the delays of executing N instructions with and without pipelining respectively are T N T T k N- 1 There is an initial delay in the pipeline execution model before each stage has operations to execute. The initial delay is usually called pipeline start-up delay P and is equal to total execution time of one instruction. The speed-up of a pipelined machine relative to a nonpipelined machine is calculated as P N P N- 1 When N is much larger than the number of pipestages P the ideal speed-up approaches P. This is an intuitive result since there are P parts of the machine working in parallel allowing the execution to go about P times faster in ideal conditions. The overlap of sequential instructions in a processor pipeline is shown in Fig. b . The instruction pipeline becomes full after the pipeline delay of P 5 cycles. Although the pipeline configuration executes operations in each stage of the processor two important mechanisms are constructed to ensure correct functional operation between dependent instructions in the presence of data hazards. Data hazards occur when instructions in the pipeline generate results that are necessary for later instructions that are already started in the pipeline. In the pipeline configuration of Fig. a register operands are initially retrieved during the decode stage. However the execute and memory stage can define register operands and contain the correct current value but are not able to update the register file until the later write-back execution stage. Forwarding or bypassing is the action of retrieving the correct operand value for an executing .
