Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article A Programmable, Scalable-Throughput Interleaver | Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2010 Article ID513104 16 pages doi 2010 513104 Research Article A Programmable Scalable-Throughput Interleaver E. J. C. Rijshouwer1 and C. H. van Berkel1 2 1 ST-Ericsson DSP Innovation Center High Tech Campus 41 5656 AE Eindhoven The Netherlands 2 System Architecture and Networking Group Department of Mathematics Computer Science Eindhoven University of Technology TU e . Box513 5600 MB Eindhoven The Netherlands Correspondence should be addressed to E. J. C. Rijshouwer Received 9 October 2009 Revised 28 December 2009 Accepted 13 March 2010 Academic Editor Dake Liu Copyright 2010 E. J. C. Rijshouwer and C. H. van Berkel. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. The interleaver stages of digital communication standards show a surprisingly large variation in throughput state sizes and permutation functions. Furthermore data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. Multistream operation for Software Defined Radio and iterative decoding algorithms will call for ever higher interleave data rates. Our interleave machine is built around 8 single-port SRAM banks and can be programmed to generate up to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts with an efficient resolution of bank conflicts. A wide range of cellular connectivity and broadcast interleavers have been mapped on this machine with throughputs up to more than Gsymbol second. Although it was designed for channel interleaving the application domain of the interleaver extends also to Turbo interleaving. The presented configuration of the architecture is designed as a part of a programmable outer .
